Amid the rapid evolution of the biometric recognition industry, the deep coupling of algorithm capabilities and chip computing power is becoming a key variable that determines product competitiveness. The QianCore and KunCore series of dedicated processors independently developed by Homsh undertake two core capabilities respectively: real-time recognition at the edge and large-scale database matching in the cloud, building a complete edge-cloud integrated iris recognition chip system.
I. Why Dedicated Chips?
Over the past decade, the iris recognition industry has long relied on general-purpose processors (ARM Cortex-A series) or Image Signal Processors (ISP) to run recognition algorithms. While this approach is manageable in consumer electronics scenarios, it has obvious bottlenecks in multiple key dimensions.
Stringent Real-Time Requirements: In scenarios such as rail transit turnstiles and airport express clearance, the latency of a single recognition must be controlled within 500ms; general-purpose processors often exceed 800ms in low-power mode, directly impairing the access experience.
Strict Power Consumption Constraints: Industrial IoT terminals and outdoor border equipment usually rely on solar or battery power supply. The full-load power consumption of general-purpose processors (5–15W) far exceeds the acceptable upper limit, restricting the feasibility of remote deployment.
Non-Negotiable Data Security Red Lines: Government, judicial and military scenarios require that iris features never leave the edge side. The open firmware of general-purpose chips has potential security risks and cannot meet the requirements of Classified Protection Level 3 and above.
It is these three constraints that have driven Homsh onto the path of independent chip R&D — resulting in two product lines with distinct positioning and mutual collaboration: QianCore and KunCore.
II. QianCore Architecture: Algorithm-Driven Hardware Design Philosophy
The core design concept of the QianCore series is "algorithm first, hardware adaptation": first accurately decompose the computation graph of the Phaselirs™ algorithm, then design targeted hardware acceleration units, rather than forcibly porting the algorithm onto a general-purpose chip.
Phase Iris Acceleration Engine (PIAE)
The core computation of the Phaselirs™ algorithm includes two major steps: Gabor filtering and phase encoding, both of which are intensive matrix operations. QianCore integrates a dedicated Phase Iris Acceleration Engine (PIAE) on-chip:
●Through three-stage pipeline parallelization, it executes image preprocessing, iris localization and feature extraction in an overlapping manner, increasing throughput by 2.8×;
●It implements INT8 fixed-point acceleration tailored to the numerical characteristics of Phaselirs™, improving the energy efficiency ratio by 4.1× with an accuracy loss of less than 0.03%;
●Built-in 512KB dedicated SRAM cache keeps iris feature templates on-chip at all times, completely eliminating the external DRAM bandwidth bottleneck.
Hardware-Level Trusted Execution Environment (TEE-H)
Different from the software-level isolation of ARM TrustZone, QianCore implements a hardware-level Trusted Execution Environment (TEE-H): the generation and matching of iris feature vectors are completed entirely in a physically isolated security domain throughout the process. It supports SM4 national cipher encrypted storage, complying with the requirements of GB/T 39786-2021; the Physical Unclonable Function (PUF) technology generates a unique chip key, fundamentally preventing firmware cloning and key extraction attacks.
Adaptive Image Quality Control (AQCC)
In real acquisition environments, illumination fluctuations, motion blur and occlusion are the three major factors affecting recognition accuracy. The AQCC module integrated in QianCore evaluates the quality of collected frames in real time before the main processing pipeline, and automatically makes decisions to trigger light supplementation, re-acquisition or degraded matching, increasing the effective frame rate to over 92%.
III. Dual Chip Product Portfolio, Covering Full Edge-Cloud Scenarios
QianCore Q80 (Edge Side)
Real-Time · Offline · Zero Data Exfiltration from the Edge
QianCore Q80 is Homsh's flagship dedicated processor built for edge deployment scenarios. Designed for access control terminals, turnstiles, handheld devices, modules and other form factors, it runs the entire inference process of the Phaselirs™ algorithm completely on the edge side. Iris feature data never leaves the device throughout the process, meeting the most stringent data sovereignty requirements.
●Single recognition latency ≤380ms (industry average: 600–900ms)
●Standby power consumption <0.8W (industry average: 2.5–5W)
●False Acceptance Rate (FAR) <0.0001%
●Operating temperature: -40°C ~ +75°C
●Data exfiltration from the edge side: Disabled (full edge-side processing)
KunCore K30 (Cloud Side)
1:N Large-Scale Database Matching · Hundred-Million-Level Retrieval · High Concurrency
KunCore K30 is a dedicated matching acceleration chip developed by Homsh for cloud and server scenarios. Its core mission is to support ultra-large-scale 1:N iris retrieval in government-level and national-level Automated Biometric Identification Systems (ABIS). After QianCore Q80 completes feature extraction on the edge side, the encrypted feature vector is uploaded to the back-end, where KunCore K30 completes high-concurrency matching against a hundred-million-level database in the cloud.
● Massive concurrency: supports real-time 1:N matching against a personnel database of ten million to hundred million entries
● High-reliability cluster: multi-card horizontal scaling with 99.99% service availability
● Domestic compliance: full-link national cipher algorithms, certified by the State Cryptography Administration
● Deployment forms: government cloud / private cloud / on-premise data center
IV. Edge-Cloud Integration: The Collaborative Architecture of QianCore and KunCore
QianCore and KunCore are not two isolated products, but two nodes of a complete edge-cloud integrated iris recognition computing architecture:
[ Collection Terminal (Camera / NIR) ] → [ QianCore Q80 (Edge Inference · Zero Edge Data Exfiltration) ] → Encrypted Feature Upload → [ KunCore K30 (Hundred-Million-Level 1:N Retrieval) ] → Matching Result Distribution
The strategic value of this architecture lies in: securing the security boundary at the edge side, while leveraging unlimited computing scalability in the cloud — it not only guarantees data sovereignty, but also achieves unlimited horizontal expansion capability.
V. Industrial Significance: From Dependence to Independent and Controllable
In the past, domestic iris recognition manufacturers were highly dependent on overseas suppliers (such as TI OMAP and NXP i.MX series) at the chip level. Against the backdrop of tightening export controls, supply chain stability faced significant hidden dangers.
The mass production of QianCore Q80 and KunCore K30 marks that Homsh has completed a full-stack independent layout from algorithm → module → chip, and achieved independent and controllable capabilities in both edge and cloud dimensions simultaneously:
● Supply Chain Security: The core computing unit does not rely on a single overseas supplier, providing reliable long-term guarantees for critical infrastructure customers.
● Customization Flexibility: The algorithm acceleration ratio, security level and interface protocol can be flexibly adjusted according to customer needs, shortening the customization cycle from the industry average of 6 months to 6 weeks.
● Ecosystem Collaboration: Deeply coupled with the OVAI software platform, hardware OTA upgrades and algorithm version iterations are promoted synchronously to protect customers' long-term investment.
QianCore Q80 secures the edge, while KunCore K30 powers the cloud. As two integral sides of the same system, these two chips jointly form the core carrier of Homsh's strategy of "independent algorithms × independent chips", marking a critical step in building its technological moat in the era of edge-cloud collaboration.
