Recently, Homsh’s R&D team completed the three-tier cascade integration of the MD31 binocular capture module, RK3588 edge computing platform and AXU9EGB FPGA accelerator board, and released a phased technical report. From the capture of a 640×480 grayscale eye image by the camera, through quality assessment, iris localization, feature inference, 1:N matching, to the display of recognition results back on screen — this entire pipeline now runs fully across three hardware boards.
For Homsh, this is more than just another successful integration test. It means we have migrated the iris recognition capabilities previously running on Windows industrial PCs into an edge architecture with lower power consumption, more flexible form factors, and the ability to be embedded into various terminal devices.
The entire system adopts a cascade architecture: capture and cropping by MD31 camera, access and transmission by RK3588, inference by AXU9EGB FPGA, and visual feedback by RK3588. The MD31 outputs cropped single-eye images for both left and right eyes; the RK3588 runs on Android ARM64, responsible for binocular pairing, task management and network transmission; the FPGA handles the quality gate and all iris algorithms, and sends results back to the RK3588 for display.
This division of labor carries deeper meaning: camera capture and FPGA inference are fully decoupled, connected by a unified protocol semantic layer. Each set of left and right eye images is associated with an operation ID and a strictly incrementing sequence number, ensuring no confusion between preview frames, retry frames and frames from previous tasks. As a result, both our legacy Windows solution and the new RK3588 solution share the same set of FPGA protocols and inference result definitions, with one set of on-board services supporting two generations of host systems.
Overall data flow of the three-tier cascade
The FPGA returns quality status, candidate identities, similarity scores, distances, thresholds and stage durations together, making the entire recognition process fully visible to users.
The heaviest part of the pipeline lies on the AXU9EGB. Based on the Zynq UltraScale+ MPSoC FPGA board, and enabled by Vitis AI 3.0 and DPU hardware acceleration, it undertakes the complete seven-step inference pipeline: from input validation, pupil and iris localization via six-parameter circular model, quality gating, Daugman polar coordinate unwrapping, to 512-dimensional iris feature generation by the IResNet100 deep network, 1:N matching after L2 normalization, and finally returning results along with per-stage latency.
Enabling a hundred-layer deep network to stably extract features on FPGA relies on strict alignment between model quantization, calibration datasets and real camera image distributions, as well as a custom zero-copy acceleration backend for the circular model. This is exactly what Homsh has been doing for 15 years: embedding algorithms into hardware, so that recognition happens as close to the device as possible.
Seven-step on-board inference pipeline on FPGA
Images failing quality checks are rejected at the third step, avoiding wasted feature computation. 512-dimensional iris feature vector — 7-step on-board inference pipeline — 326 cumulative tests passed
In terms of usage logic, the system adheres to the principle of "strict registration, flexible recognition". During registration, both left and right eye templates of the user must pass the quality gate and be successfully enrolled; failed frames, duplicate eye sides and unknown eye sides are excluded from the registration count. During recognition, by contrast, left and right eyes are inferred separately and matched 1:N against left and right eye templates in the template library respectively. A match from any single query eye image against any template returns a result — users do not need to position both eyes for the system; whichever eye is captured is processed.
Quality failures, temporary mismatches or recoverable communication errors do not abruptly terminate the task. The system retains task state and continues waiting for the next set of images; after connection recovery, it resumes from the operation ID and acknowledged sequence numbers without resubmitting frames already received by the FPGA. Every step of recognition — quality, similarity, distance, threshold, latency — is fed back to the interface, making success, failure and retries visible to users.
Registration requires complete binocular templates, while recognition only needs a match from either eye, balancing security and user experience.
What we are most proud of in this phased report is actually its methodology. Every verification conclusion is clearly categorized into four types: "Verified" for reproducible test results, "Historically Verified" from previous integration records, "Inferred" derived from implementation logic, and honestly marked "To Be Verified" for temporarily unconfirmed items. The 176 automated tests on the Windows baseline all passed, 150 on-board Python tests passed, and registration/recognition and connection recovery functions completed integration — all these are documented in the report. Items not yet re-tested on site are also clearly marked "To Be Verified" in black and white, with no ambiguity.
Iris recognition is the business of identity, leaving no room for "probably fine". Documenting uncertainties on paper is our commitment to our customers, and to ourselves.
Three key figures: 512-dimensional features generated via DPU acceleration; all 176 automated Windows baseline tests passed; 150 on-board Python test records passed.
The overall judgment of the report is that the current solution has laid the foundation for phased demonstration, integration and documentation, with clear architectural boundaries and technically feasible overall cascade architecture. The next priorities are equally clear: end-to-end stability, real-time image quality, polar coordinate unwrapping consistency, and closed-loop state monitoring for long-term operation, moving the pipeline from "functional" to "stable and reliable", and then to production-ready products.
From self-developed iris recognition chips, to software-hardware synergy between algorithms and FPGAs, to today’s complete recognition pipeline embedded in edge devices, Homsh has always believed that the future of biometrics lies at the edge. This phased report is another step toward that future.
